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| ADC1015S series Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 01 -- 12 April 2010 Preliminary data sheet 1. General description The ADC1015S is a single channel 10-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1015S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. The ADC1015S supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1015S is ideal for use in communications, imaging and medical applications - especially in high Intermediate Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range. 2. Features and benefits SNR, 61.7 dBFS / SFDR, 86 dBc Sample rate up to 125 Msps 10-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Integrated input buffer Flexible input voltage range: 1 V (p-p) to 2 V (p-p) CMOS or LVDS DDR digital outputs Pin compatible with the ADC1415S series, the ADC1215S series and the ADC1115S125 HVQFN40 package Input bandwidth, 600 MHz Power dissipation, 635 mW at 80 Msps, including analog input buffer SPI Duty cycle stabilizer Fast OuT of Range (OTR) detection INL 1.25 LSB, DNL 0.25 LSB Offset binary, two's complement, gray code Power-down and Sleep modes NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 3. Applications Wireless and wired broadband communications Portable instrumentation Imaging systems Digital predistortion loop, power amplifier linearization Spectral analysis Ultrasound equipment Software defined radio 4. Ordering information Table 1. Ordering information fs (Msps) Package Name ADC1015S125HN/C1 125 ADC1015S105HN/C1 105 ADC1015S080HN/C1 80 ADC1015S065HN/C1 65 Description Version SOT618-6 SOT618-6 SOT618-6 SOT618-6 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm Type number ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 2 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 5. Block diagram SDIO/ODS CS SCLK/DFS ADC1015S ERROR CORRECTION AND DIGITAL PROCESSING SPI OTR INP INPUT BUFFER INM S/H INPUT STAGE ADC CORE 10-BIT PIPELINED OUTPUT DRIVERS CMOS: D9 to D0 or LVDS/DDR: D9P, D9M to D0P, D0M CMOS: DAV or LVDS/DDR: DAVP DAVM OUTPUT DRIVERS CLOCK INPUT STAGE AND DUTY CYCLE CONTROL SYSTEM REFERENCE AND POWER MANAGEMENT PWD OE CLKP CLKM VREF REFB VCM SENSE REFT 005aaa143 Fig 1. Block diagram ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 3 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 6. Pinning information 6.1 Pinning 36 SCLK/DFS 37 SDIO/ODS 36 SCLK/DFS 37 SDIO/ODS 39 SENSE 34 OGND 33 VDDO 40 VREF 35 OTR 39 SENSE 34 OGND 33 VDDO 40 VREF 35 OTR 38 CS terminal 1 index area REFB REFT AGND VCM VDDA5V AGND INM INP AGND 1 2 3 4 5 6 7 8 9 31 DAV 32 n.c. REFB 30 n.c. 29 n.c. 28 n.c. 27 n.c. 26 D0 25 D1 24 D2 23 D3 22 D4 21 D5 REFT AGND VCM VDDA5V AGND INM INP AGND 1 2 3 4 5 6 7 8 9 38 CS terminal 1 index area 31 DAV 30 n.c. 29 n.c. 28 n.c. 27 n.c. 26 D0_D1_P 25 D0_D1_M 24 D2_D3_P 23 D2_D3_M 22 D4_D5_P 21 D4_D5_M D6_D7_P 20 005aaa145 ADC1015S HVQFN40 ADC1015S HVQFN40 VDDA3V 10 VDDA3V 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D8_D9_M 17 D8_D9_P 18 D6_D7_M 19 VDDA3V 10 VDDA3V 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D9 17 D8 18 D7 19 D6 20 005aaa144 Transparent top view Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected Fig 3. Pin configuration with LVDS/DDR digital outputs selected 6.2 Pin description Table 2. Symbol REFB REFT AGND VCM VDDA5V AGND INM INP AGND VDDA3V VDDA3V CLKP CLKM DEC OE PWD ADC1015S_SER_1 Pin description (CMOS digital outputs) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type [1] O O G O P G I I G P P I I O I I Description bottom reference top reference analog ground common-mode output voltage 5 V analog power supply analog ground complementary analog input analog input analog ground 3 V analog power supply 3 V analog power supply clock input complementary clock input regulator decoupling node output enable, active LOW power down, active HIGH (c) NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 01 -- 12 April 2010 32 n.c. 4 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Pin description (CMOS digital outputs) Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Type [1] O O O O O O O O O O O P G O I I/O I I I/O Description data output bit 9 (MSB) data output bit 8 data output bit 7 data output bit 6 data output bit 5 data output bit 4 data output bit 3 data output bit 2 data output bit 1 data output bit 0 (LSB) not connected not connected not connected not connected data valid output clock not connected output power supply output ground out of range SPI clock / data format select SPI data IO / output data standard SPI chip select reference programming pin voltage reference input/output Table 2. Symbol D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c. n.c. n.c. n.c. DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Symbol D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P n.c. n.c. n.c. Pin description (LVDS/DDR) digital outputs) Pin [1] 17 18 19 20 21 22 23 24 25 26 27 28 29 Type [2] O O O O O O O O O O Description differential output data D8 and D9 multiplexed, complement differential output data D8 and D9 multiplexed, true differential output data D6 and D7 multiplexed, complement differential output data D6 and D7 multiplexed, true differential output data D4 and D5 multiplexed, complement differential output data D4 and D5 multiplexed, true differential output data D2 and D3 multiplexed, complement differential output data D2 and D3 multiplexed, true differential output data D0 and D1 multiplexed, complement differential output data D0 and D1 multiplexed, true not connected not connected not connected ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 5 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Pin description ...continued (LVDS/DDR) digital outputs) Pin [1] 30 31 32 Type [2] O O Description not connected data valid output clock, complement data valid output clock, true Table 3. Symbol n.c. DAVM DAVP [1] [2] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VO Parameter output voltage Conditions pins D9 to D0 or pins D9P to D0P and D9M to D0M on pin VDDA3V on pin VDDA5V VDDA(3V) - VDDO Min -0.4 Max +3.9 Unit V VDDA(3V) VDDA(5V) VDDO VCC Tstg Tamb Tj analog supply voltage 3 V analog supply voltage 5 V output supply voltage supply voltage difference storage temperature ambient temperature junction temperature -0.5 -0.5 -0.5 +4.6 +4.6 +4.6 V V V V C C C 8. Thermal characteristics Table 5. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions [1] [1] Typ 30.5 13.3 Unit K/W K/W Value for six layers board in still air with a minimum of 25 thermal vias. ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 6 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 9. Static characteristics Table 6. Symbol Supplies VDDA(5V) VDDA(3V) VDDO IDDA(5V) IDDA(3V) IDDO analog supply voltage 5 V analog supply voltage 3 V output supply voltage analog supply current 5 V analog supply current 3 V output supply current CMOS mode LVDS DDR mode fclk = 125 Msps; fi =70 MHz fclk = 125 Msps; fi =70 MHz CMOS mode; fclk = 125 Msps; fi =70 MHz LVDS DDR mode: fclk = 125 Msps; fi =70 MHz P power dissipation ADC1015S125; analog supply only ADC1015S105; analog supply only ADC1015S080; analog supply only ADC1015S065; analog supply only Power-down mode Standby mode Clock inputs: pins CLKP and CLKM LVPECL Vi(clk)dif LVDS Vi(clk)dif SINE wave Vi(clk)dif LVCMOS VIL VIH VIL VIH IIL IIH LOW-level input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current 0.7VDDA(3V) 0 2 - 35 - mA - 840 770 635 580 2 40 - mW mW mW mW mW mW Logic inputs: pins PWD and OE ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 7 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Table 6. Symbol VIL VIH IIL IIH CI Static characteristics[1] ...continued Parameter LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance Conditions Min 0 0.7VDDA(3V) -10 -50 Typ 4 Max 0.3VDDA(3V) VDDA(3V) +10 +50 Unit V V A A pF Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS Digital outputs, CMOS mode: pins D9 to D0, OTR, DAV Output levels, VDDO = 3 V VOL VOH IOL IOH CO LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current output capacitance IOL = Output levels, VDDO = 1.8 V VOL VOH LOW-level output voltage HIGH-level output voltage OGND 0.8VDDO 0.2VDDO VDDO V V Digital outputs, LVDS mode: pins D9P to D0P, D9M to D0M, DAVP and DAVM Output levels, VDDO = 3 V only, Rload = 100 VO(offset) VO(dif) CO II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) output offset voltage differential output voltage output capacitance input current input resistance input capacitance common-mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current peak-to-peak VINP = VINM output buffer current set to 3.5 mA output buffer current set to 3.5 mA -5 0.9 1 0.5VDDA(3V) Analog inputs: pins INP and INM Common mode output voltage: pin VCM ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 8 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Table 6. Symbol VVREF Accuracy INL DNL Eoffset EG Supply PSRR Static characteristics[1] ...continued Parameter voltage on pin VREF Conditions output input integral non-linearity differential non-linearity offset error gain error power supply rejection ratio 100 mV (p-p) on VDDA(3V) guaranteed no missing codes Min 0.5 -0.4 -0.06 Typ 0.5 to 1 0.07 0.04 2 0.5 35 Max 1 +0.4 +0.06 Unit V V LSB LSB mV %FS dBc I/O reference voltage: pin VREF [1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 9 of 39 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Symbol Dynamic characteristics[1] Parameter Conditions ADC1015S065 Min Analog signal processing 2H second harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-tonoise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 87 86 85 82 86 85 84 81 85 84 83 80 9.9 9.9 9.9 9.9 61.7 61.6 61.6 61.5 86 85 84 81 87 86 85 82 86 85 84 81 85 84 83 80 9.9 9.9 9.9 9.9 61.7 61.6 61.6 61.5 86 85 84 81 86 86 84 81 85 85 83 80 84 84 82 79 9.9 9.9 9.9 9.9 61.6 61.6 61.5 61.5 85 85 83 80 88 87 85 83 87 86 84 82 86 85 83 81 9.9 9.9 9.9 9.9 61.6 61.6 61.5 61.5 87 86 84 82 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBFS dBFS dBFS dBFS dBc dBc dBc dBc Typ Max ADC1015S080 Min Typ Max ADC1015S105 Min Typ Max ADC1015S125 Min Typ Max Unit Preliminary data sheet Rev. 01 -- 12 April 2010 10 of 39 ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1015S series; input buffer; CMOS or LVDS DDR digital output ADC1015S series SFDR spuriousfree dynamic range fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 7. Symbol IMD Dynamic characteristics[1] ...continued Parameter Intermodulation distortion Conditions fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz [1] Preliminary data sheet Rev. 01 -- 12 April 2010 11 of 39 ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1015S065 Min Typ 89 88 87 84 Max - ADC1015S080 Min Typ 89 88 87 85 Max - ADC1015S105 Min Typ 88 88 86 83 Max - ADC1015S125 Min Typ 89 88 86 84 Max Unit dBc dBc dBc dBc Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1015S series; input buffer; CMOS or LVDS DDR digital output ADC1015S series xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.2 Clock and digital output timing Table 8. Clock and digital output timing characteristics[1] Conditions ADC1015S065 Min Clock timing input: pins CLKP and CLKM fclk tlat(data) clk td(s) clock frequency data latency time clock duty cycle sampling delay time wake-up time propagation delay set-up time hold time rise time[2] fall time[2] DATA DAV tf DATA DATA DAV DCS_EN = 1 DCS_EN = 0 20 30 45 0.5 0.5 0.5 14 50 50 0.8 Preliminary data sheet Rev. 01 -- 12 April 2010 12 of 39 ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. NXP Semiconductors twake tPD tsu th tr ADC1015S series; input buffer; CMOS or LVDS DDR digital output CMOS mode timing output: pins D9 to D0 and DAV ADC1015S series xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 8. Clock and digital output timing characteristics[1] ...continued Conditions ADC1015S065 Min tPD tsu th tr tf All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 13 of 39 ADC1015S_SER_1 NXP Semiconductors Symbol Parameter ADC1015S080 Min 50 50 50 Typ 3.9 4.2 3.5 2.0 100 100 100 200 200 200 Max 50 50 50 ADC1015S105 Min Typ 3.9 4.2 2.1 2.0 100 100 100 200 200 200 Max 50 50 50 ADC1015S125 Min Typ 3.9 4.2 1.4 2.0 100 100 100 200 200 200 Max Unit Typ 3.9 4.2 5.1 2.0 100 100 100 - Max LVDS DDR mode timing output: pins D9P to D0P, D9M to D0M, DAVP and DAVM propagation delay set-up time hold time rise time[3] DATA DAV fall time[3] DATA DATA DAV 50 50 50 ns ns ns ns ps ps ps 200 200 200 [1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Measured between 20 % to 80 % of VDDO. Rise time measured from -50 mV to +50 mV; fall time measured from +50 mV to -50 mV. ADC1015S series; input buffer; CMOS or LVDS DDR digital output [2] [3] ADC1015S series NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output N N+1 td(s) N+2 tclk CLKP CLKM tPD (N - 14) (N - 13) (N - 12) (N - 11) DATA tPD tsu DAV th tclk 005aaa060 Fig 4. CMOS mode timing N N+1 td(s) N+2 tclk CLKP CLKM tPD Dx_Dx + 1_P Dx Dx_Dx + 1_M tsu th tsu th DAVP DAVM tclk 005aaa061 (N - 14) (N - 13) (N - 12) (N - 11) Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 tPD Fig 5. LDVS DDR mode timing ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 14 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 10.3 SPI timings Table 9. Symbol tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max) [1] Characteristics Parameter SCLK pulse width SCLK pulse width HIGH SCLK pulse width LOW set-up time hold time maximum clock frequency data to SCLKH CS to SCLKH data to SCLKH CS to SCLKH Conditions Min 40 16 16 5 5 2 2 Typ Max 25 Unit ns ns ns ns ns ns ns MHz SPI timings Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified tsu CS tsu th tw(SCLKL) tw(SCLK) tw(SCLKH) th SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. SPI timing 11. Application information 11.1 Device control The ADC1015S can be controlled via the Serial Peripheral Interface (SPI) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device will remain in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 7. ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 15 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output CS Pin control mode Data format offset binary SPI control mode SCLK/DFS Data format two's complement LVDS DDR SDIO/ODS CMOS R/W W1 W0 A12 005aaa039 Fig 7. Control mode selection. When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1015S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 19) or using pins PWD and OE in Pin control mode, as described in Table 10. Table 10. Pin PWD 0 0 1 1 Operating mode selection via pin PWD and OE Pin OE 0 1 0 1 Operating mode Power-up Power-up Sleep Power-down Output high-Z no yes yes yes 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two's complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset binary or two's complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two's complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1015S supports differential or single-ended input drive. Optimal performance is achieved using differential inputs. The ADC inputs are internally biased and need to be decoupled. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 21 further details). ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 16 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8. package ESD parasitics switch INP 8 Ron = 15 4 pF internal clock INPUT BUFFER Ron = 15 sampling capacitor switch INM 7 4 pF internal clock sampling capacitor 005aaa107 Fig 8. Input sampling circuit and input buffer The integrated input buffer offers the following advantages: * The kickback effect is avoided - the charge injection and glitches generated by the S/H input stage are isolated from the input circuitry. So there's no need for additional filtering. * The input capacitance is very low and constant over a wide frequency range, which makes the ADC1015S easy to drive. The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 9 would be suitable for a baseband application. ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 17 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output ADT1-1WT Analog input 100 nF 100 nF INP 50 100 nF 100 nF INM VCM 100 nF 100 nF 005aaa108 Fig 9. Single transformer configuration suitable for baseband applications The configuration shown in Figure 10 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance. ADT1-1WT 100 nF 50 ADT1-1WT 100 nF INP Analog input 100 50 100 nF INM VCM 100 nF 100 nF 100 nF 005aaa109 Fig 10. Dual transformer configuration suitable for high intermediate frequency application ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 18 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 11.3 System reference and power management 11.3.1 Internal/external references The ADC1015S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and -6 dB via control bits INTREF[2:0] when bit INTREF_EN = 1; see Table 21). See Figure 12, Figure 13, Figure 14 and Figure 15. The equivalent reference circuit is shown in Figure 11. External reference is also possible by providing a voltage on pin VREF as described in Figure 14. REFT REFERENCE AMP REFB VREF EXT_ref BANDGAP REFERENCE BUFFER EXT_ref ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 11. Reference equivalent schematic If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in Table 11. Table 11. Selection internal (Figure 12) internal (Figure 13) external (Figure 14) internal via SPI (Figure 15) [1] ADC1015S_SER_1 Reference selection SPI bit INTREF_EN 0 0 0 1 SENSE pin AGND VREF pin 330 pF capacitor to AGND full scale (p-p) 2V 1V 1 V to 2 V 1 V to 2 V pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND VDDA(3V) external voltage between 0.5 V and 1 V[1] pin VREF connected to pin SENSE and via 330 pF capacitor to AGND The voltage on pin VREF is doubled internally to generate the internal reference voltage. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 19 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Figure 12 to Figure 15 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. VREF 330 pF VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 12. Internal reference, 2 V (p-p) full-scale Fig 13. Internal reference, 1 V (p-p) full-scale VREF 0.1 F VREF V REFERENCE EQUIVALENT SCHEMATIC 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa119 005aaa118 Fig 14. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 15. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale 11.3.2 Reference gain control The reference gain is programmable between 0 dB to -6 dB in 1 dB steps via the SPI (see Table 21). The corresponding full-scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 12: Table 12. INTREF 000 001 010 011 100 101 110 111 Reference SPI Gain Control Gain 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB reserved full scale (p-p) 2V 1.78 V 1.59 V 1.42 V 1.26 V 1.12 V 1V x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 F filter capacitor should be connected between pin VCM and ground. 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see Table 22). ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 20 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 11.4 Clock input 11.4.1 Drive modes The ADC1015S can be driven differentially (SINE, LVPECL or LVDS) with little or no degradation on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor). LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input CLKM 005aaa174 005aaa053 a. Rising edge LVCMOS Fig 16. LVCMOS single-ended clock input b. Falling edge LVCMOS CLKP Sine clock input Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVDS clock input LVPECL clock input CLKM CLKP CLKM 005aaa055 005aaa172 c. LVDS clock input Fig 17. Differential clock input d. LVPECL clock input ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 21 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode voltage of the differential input stage is set via internal 5 k resistors. PACKAGE ESD PARASITICS CLKP Vcm(clk) SE_SEL SE_SEL 5 k 5 k CLKM 005aaa056 Fig 18. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45% and 55%. 11.4.4 Clock input divider The ADC1015S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 22 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 19. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO PARASITICS ESD PACKAGE LOGIC DRIVER 50 Dx OGND 005aaa057 Fig 19. CMOS digital output buffer The output resistance is 50 and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30): ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 23 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 23). VCCO 3.5 mA typ - + DnP/Dn + 1P 100 DnM/Dn + 1M RECEIVER + - OGND 005aaa058 Fig 20. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 resistor (typical) at the receiver side (Figure 20) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 21 and Table 32). VCCO 3.5 mA typ - + DxP/Dx + 1P RECEIVER DxM/Dx + 1M 100 + - OGND 005aaa059 Fig 21. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic voltage levels. Table 13. 000 001 010 011 100 ADC1015S_SER_1 LVDS DDR output register 2 Resistor value () no internal termination 300 180 110 150 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. LVDS_INT_TER[2:0] Preliminary data sheet Rev. 01 -- 12 April 2010 24 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output LVDS DDR output register 2 ...continued Resistor value () 100 81 60 Table 13. 101 110 111 LVDS_INT_TER[2:0] 11.5.3 Data valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1015S. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively. 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1; see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The Fast OTR detection threshold (below full scale) can be programmed via bits FASTOTR_DET[2:0]. Table 14. 000 001 010 011 100 101 110 111 Fast OTR register Detection level (dB) -20.56 -16.12 -11.02 -7.82 -5.49 -3.66 -2.14 -0.86 FASTOTR_DET[2:0] 11.5.5 Digital offset By default, the ADC1015S delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 25). 11.5.6 Test patterns For test purposes, the ADC1015S can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless of the analog input. ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 25 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 11.5.7 Output codes versus input voltage Table 15. VINP - VINM < -1 -1.0000000 -0.9980469 -0.9960938 -0.9941406 -0.9921875 .... -0.0039063 -0.0019531 0.0000000 +0.0019531 +0.0039063 .... +0.9921875 +0.9941406 +0.9960938 +0.9980469 +1.0000000 > +1 Output codes Offset binary 00 0000 0000 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0011 00 0000 0100 .... 01 1111 1110 01 1111 1111 10 0000 0000 10 0000 0001 10 0000 0010 .... 11 1111 1011 11 1111 1100 11 1111 1101 11 1111 1110 11 1111 1111 11 1111 1111 Two's complement 10 0000 0000 10 0000 0000 10 0000 0001 10 0000 0010 10 0000 0011 10 0000 0100 .... 11 1111 1110 11 1111 1111 00 0000 0000 00 0000 0001 00 0000 0010 .... 01 1111 1011 01 1111 1100 01 1111 1101 01 1111 1110 01 1111 1111 01 1111 1111 OTR pin 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 11.6 Serial peripheral interface 11.6.1 Register description The ADC1015S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 17). Table 16. Bit Description Instruction bytes for the SPI MSB 7 R/W[1] A7 [1] [2] LSB 6 W1[2] A6 5 W0[2] A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0 Bit R/W indicates whether it is a read (1) or a write (0) operation. Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17). ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 26 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Number of data bytes to be transferred after the instruction bytes W0 0 1 0 1 Number of bytes transmitted 1 byte 2 bytes 3 bytes 4 bytes or more Table 17. W1 0 0 1 1 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end on data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction bytes Register N (data) Register N + 1 (data) 005aaa062 Fig 22. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization, it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1015S enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 23). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 23. When the ADC1015S enters SPI control mode, the output data format (two's complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] in Table 23. ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 27 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 24. Default mode at start-up: SCLK HIGH = two's complement; SDIO LOW = CMOS ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 28 of 39 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 11.6.3 Register allocation map Table 18. Register allocation map R/W R/W R/W Bit definition Bit 7 0005 0006 0008 0010 Reset and operating mode Clock SW_RST TESTPAT_USER[9:2] TESTPAT_ USER[1:0] DAVI_ x2_EN DAVI[1:0] BIT_BYTE_WISE FASTOTR DAV_DRV[1:0] DATAI_x2_EN FASTOTR_DET[2:0] DATA_DRV[1:0] DATAI[1:0] Bit 6 Bit 5 Bit 4 Bit 3 DIFF_SE INTREF_EN OUTBUF DAVINV DIG_OFFSET[5:0] TESTPAT_SEL[2:0] OUTBUS_SWAP Bit 2 Bit 1 Bit 0 OP_MODE[1:0] CLKDIV INTREF[2:0] IB_IBIAS[1:0] DCS_EN RESERVED[2:0] SE_SEL LVDS_ CMOS Default Bin 0000 0000 0000 0001 0000 0000 0000 0011 0000 0000 0000 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 0000 0000 0000 0000 AddrHex Register name Preliminary data sheet Rev. 01 -- 12 April 2010 29 of 39 ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. NXP Semiconductors Internal reference R/W Input buffer Output data standard. Output clock Offset Test pattern 1 Test pattern 2 Test pattern 3 Fast OTR CMOS output R/W R/W R/W R/W R/W R/W R/W R/W R/W 0011 0012 0013 0014 0015 0016 0017 0020 0021 0022 DATA_FORMAT[1:0] ADC1015S series; input buffer; CMOS or LVDS DDR digital output DAVPHASE[2:0] ADC1015S series LVDS DDR O/P 1 R/W LVDS DDR O/P 2 R/W LVDS_INT_TER[2:0] NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Table 19. Bit 7 Reset and operating mode control register (address 0005h) bit description Symbol SW_RST Access R/W 0 1 Value Description reset digital section no reset performs a reset on SPI registers reserved not used operating mode 00 01 10 11 normal (Power-up) Power-down Sleep normal (Power-up) 6 to 4 3 to 2 1 to 0 RESERVED[2:0] OP_MODE[1:0] R/W 000 00 Table 20. Bit 7 to 5 4 - Clock control register (address 0006h) bit description Symbol SE_SEL Access R/W 0 1 Value 000 Description not used single-ended clock input pin select CLKM CLKP differential/single ended clock input select 0 1 fully differential single-ended not used clock input divide by 2 0 1 disabled enabled duty cycle stabilizer 0 1 disabled enabled 3 DIFF_SE R/W 2 1 CLKDIV R/W 0 0 DCS_EN R/W ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 30 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Table 21. Bit 7 to 4 3 - Internal reference control register (address 0008h) bit description Symbol INTREF_EN Access R/W 0 1 Value 0000 Description not used programmable internal reference enable disable active programmable internal reference 000 001 010 011 100 101 110 111 0 dB (FS = 2 V) -1 dB (FS = 1.78 V) -2 dB (FS = 1.59 V) -3 dB (FS = 1.42 V) -4 dB (FS = 1.26 V) -5 dB (FS = 1.12 V) -6 dB (FS = 1 V) reserved 2 to 0 INTREF[2:0] R/W Table 22. Bit 7 to 2 1 to 0 - Input buffer control register (address 0010h) bit description Symbol IB_IBIAS[1:0] Access R/W 00 01 10 11 Value 000000 Description not used input buffer bias current not used medium low high Table 23. Bit 7 to 5 4 - Output data standard control register (address 0011h) bit description Symbol LVDS_CMOS Access R/W 0 1 Value 000 Description not used output data standard: LVDS DDR or CMOS CMOS LVDS DDR output buffers enable 0 1 output enabled output disabled (high Z) output bus swapping 0 1 no swapping output bus is swapped (MSB becomes LSB and vice versa) output data format 00 01 10 11 offset binary two's complement gray code offset binary 3 OUTBUF R/W 2 OUTBUS_SWAP R/W 1 to 0 DATA_FORMAT[1:0] R/W ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 31 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Table 24. Bit 7 to 4 3 - Output clock register (address 0012h) bit description Symbol DAVINV Access R/W 0 1 Value 0000 Description not used output clock data valid (DAV) polarity normal inverted DAV phase select 000 001 010 011 100 101 110 111 output clock shifted (ahead) by 3 ns output clock shifted (ahead) by 2.5 ns output clock shifted (ahead) by 2 ns output clock shifted (ahead) by 1.5 ns output clock shifted (ahead) by 1 ns output clock shifted (ahead) by 0.5 ns default value as defined in timing section output clock shifted (delayed) by 0.5 ns 2 to 0 DAVPHASE[2:0] R/W Table 25. Bit 7 to 6 5 to 0 - Offset register (address 0013h) bit description Symbol DIG_OFFSET[5:0] Access R/W 011111 ... 000000 ... 100000 ... 0 ... -32 LSB Value 00 Description not used digital offset adjustment +31 LSB Table 26. Bit 7 to 3 2 to 0 - Test pattern register 1 (address 0014h) bit description Symbol TESTPAT_SEL[2:0] Access R/W 000 001 010 011 100 101 110 111 Value 00000 Description not used digital test pattern select off mid scale -FS +FS toggle `1111..1111'/'0000..0000' custom test pattern `1010..1010.' `010..1010' Table 27. Bit 7 to 0 Test pattern register 2 (address 0015h) bit description Symbol TESTPAT_USER[9:2] Access R/W Value 00000000 Description custom digital test pattern (bits 9 to 2) ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 32 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Table 28. Bit 7 to 6 5 to 0 Table 29. Bit 7 to 4 3 - Test pattern register 3 (address 0016h) bit description Symbol TESTPAT_USER[1:0] Access R/W Value 00 000000 Description custom digital test pattern (bits 1 to 0) not used Fast OTR register (address 0017h) bit description Symbol FASTOTR Access R/W 0 1 Value 0000 Description not used fast Out-of-Range (OTR) detection disabled enabled set fast OTR detect level 000 001 010 011 100 101 110 111 -20.56 dB -16.12 dB -11.02 dB -7.82 dB -5.49 dB -3.66 dB -2.14 dB -0.86 dB 2 to 0 FASTOTR_DET[2:0] R/W Table 30. Bit 7 to 4 3 to 2 - CMOS output register (address 0020h) bit description Symbol DAV_DRV[1:0] Access R/W 00 01 10 11 Value 0000 Description not used drive strength for DAV CMOS output buffer low medium high very high drive strength for DATA CMOS output buffer 00 01 10 11 low medium high very high 1 to 0 DATA_DRV[1:0] R/W ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 33 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output Table 31. Bit 7 to 6 5 - LVDS DDR output register 1 (address 0021h) bit description Symbol DAVI_x2_EN Access R/W 0 1 Value 00 Description not used double LVDS current for DAV LVDS buffer disabled enabled LVDS current for DAV LVDS buffer 00 01 10 11 3.5 mA 4.5 mA 1.25 mA 2.5 mA double LVDS current for DATA LVDS buffer 0 1 disabled enabled LVDS current for DATA LVDS buffer 00 01 10 11 3.5 mA 4.5 mA 1.25 mA 2.5 mA 4 to 3 DAVI[1:0] R/W 2 DATAI_x2_EN R/W 1 to 0 DATAI[1:0] R/W Table 32. Bit 7 to 4 3 - LVDS DDR output register 2 (address 0022h) bit description Symbol BIT/BYTE_WISE Access R/W 0 1 Value 0000 Description not used DDR mode for LVDS output bit wise (even data bits output on DAV rising edge / odd data bits output on DAV falling edge) byte wise (MSB data bits output on DAV rising edge / LSB data bits output on DAV falling edge) internal termination for LVDS buffer (DAV and DATA) 000 001 010 011 100 101 110 111 no internal termination 300 180 110 150 100 81 60 2 to 0 LVDS_INTTER[2:0] R/W ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 34 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-6 D B A terminal 1 index area E A A1 c detail X e1 1/2 e e 11 L 10 21 e b 20 v w CAB C y1 C C y Eh 1/2 e e2 1 terminal 1 index area 40 Dh 31 30 X 0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 6.1 6.0 5.9 Dh 4.55 4.40 4.25 E(1) 6.1 6.0 5.9 Eh 4.55 4.40 4.25 e 0.5 2.5 scale e1 4.5 e2 4.5 L 0.5 0.4 0.3 5 mm v 0.1 w y y1 0.1 max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT618-6 References IEC JEDEC MO-220 JEITA --European projection sot618-6_po Issue date 09-02-23 09-03-04 Fig 25. Package outline SOT618-6 (HVQFN40) ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 35 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 13. Revision history Table 33. Revision history Release date 20100412 Data sheet status Preliminary data sheet Change notice Supersedes Document ID ADC1015S_SER_1 ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 36 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 14. Legal information 14.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. 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Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. (c) NXP B.V. 2010. All rights reserved. 14.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 01 -- 12 April 2010 37 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1015S_SER_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 01 -- 12 April 2010 38 of 39 NXP Semiconductors ADC1015S series ADC1015S series; input buffer; CMOS or LVDS DDR digital output 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Clock and digital output timing . . . . . . . . . . . . 12 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 15 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI and Pin control modes . . . . . . . . . . . . . . . 15 Operating mode selection. . . . . . . . . . . . . . . . 16 Selecting the output data standard . . . . . . . . . 16 Selecting the output data format. . . . . . . . . . . 16 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System reference and power management . . 19 Internal/external references . . . . . . . . . . . . . . 19 Reference gain control . . . . . . . . . . . . . . . . . . 20 Common-mode output voltage (VO(cm)) . . . . . 20 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 21 Equivalent input circuit . . . . . . . . . . . . . . . . . . 22 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 22 Clock input divider . . . . . . . . . . . . . . . . . . . . . 22 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 23 Digital output buffers: CMOS mode . . . . . . . . 23 Digital output buffers: LVDS DDR mode . . . . . 24 Data valid (DAV) output clock . . . . . . . . . . . . . 25 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 25 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output codes versus input voltage . . . . . . . . . 26 Serial peripheral interface. . . . . . . . . . . . . . . . 26 Register description . . . . . . . . . . . . . . . . . . . . 26 Default modes at start-up . . . . . . . . . . . . . . . . 27 Register allocation map . . . . . . . . . . . . . . . . . 29 12 13 14 14.1 14.2 14.3 14.4 15 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 37 37 37 37 38 38 39 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 April 2010 Document identifier: ADC1015S_SER_1 |
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